1. Field of the Invention
The present invention relates generally to semiconductor wafers, and more particularly to methods for the gas plasma etching of backside through vias on semiconductor wafers, especially thinned semiconductor wafers.
2. Discussion of the Related Art
Semiconductors are generally defined as materials having an electrical conductivity intermediate between metals and insulators and are used in a wide variety of modern electronic devices. The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit are formed on a single wafer.
Generally, the process involves the creation of eight to 20 patterned layers on and into the substrate, ultimately forming the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface.
The first step in semiconductor manufacturing begins with production of a wafer, i.e., a thin, round slice of a semiconductor material, usually silicon. Other suitable semiconductor materials include gallium arsenide (GaAs) and indium phosphide (InP).
A silicon wafer, for example, purified polycrystalline silicon, is created from sand, is heated to a molten liquid. A small piece of solid silicon (seed) is placed on the molten liquid, and as the seed is slowly pulled from the melt the liquid cools to form a single crystal ingot. The surface tension between the seed and molten silicon causes a small amount of the liquid to rise with the seed and cool.
The crystal ingot is then ground to a uniform diameter and a diamond saw blade cuts the ingot into thin wafers. The wafer is processed through a series of machines, where it is ground smooth and chemically polished to a mirror-like luster. The wafers are then ready to be sent to the wafer fabrication area where they are used as the starting material for manufacturing integrated circuits.
The heart of semiconductor manufacturing is the wafer fabrication facility where the integrated circuit is formed in and on the wafer. The fabrication process, which takes place in a clean room, involves a series of principal steps described below. Typically, it takes from 10 to 30 days to complete the fabrication process.
Wafers are pre-cleaned using high purity, low particle chemicals (important for high-yield products). The silicon wafers are heated and exposed to ultra-pure oxygen in the diffusion furnaces under carefully controlled conditions forming a silicon dioxide film of uniform thickness on the surface of the wafer.
Masking is used to protect one area of the wafer while working on another. This process is referred to as photolithography or photo-masking. A photoresist or light-sensitive film is applied to the wafer, giving it characteristics similar to a piece of photographic paper. A photo-aligner aligns the wafer to a mask and then projects an intense light through the mask and through a series of reducing lenses, exposing the photoresist with the mask pattern. Precise alignment of the wafer to the mask prior to exposure is critical; thus, most alignment tools are fully automatic.
The wafer is then “developed” (the exposed photoresist is removed) and baked to harden the remaining photoresist pattern. It is then exposed to a chemical solution (i.e., wet etching) or a plasma gas discharge (i.e., dry etching) so that areas not covered by the hardened photoresist are etched away. Wet etching is the process of removing exposed silicon dioxide in the pattern created by photoresist exposure and development with a liquid, typically an organic acid. In dry etching, reactive gas plasma is used in place of a wet etching solution. Dry etching provides a higher resolution than wet etching and therefore is more likely to be used as circuit elements become smaller. Dry etching generally produces less “undercutting” of the wafer substrate under photoresist, often provides more control over etching rate, and may be necessary where the etched layer is resistant to liquid etchants. Gaseous etching is generally performed with halogenated compounds which, depending on the wafer substrate, may be bromine, chlorine, fluorine or iodine-based gases in a carrier gas. The photoresist is removed using additional chemicals or plasma and the wafer is inspected to ensure the image transfer from the mask to the top layer is correct.
Atoms with one less electron than silicon (such as boron), or one more electron than silicon (such as phosphorous), are introduced into the area exposed by the etch process to alter the electrical character of the silicon. These areas are called P-type (boron) or N-type (phosphorous) to reflect their conducting characteristics.
The thermal oxidation, masking etching and doping steps are repeated several times until the last “front end” layer is completed (i.e., all active devices have been formed).
Following completion of the “front end,” the individual devices are interconnected using a series of metal depositions and patterning steps of dielectric films (insulators). Current semiconductor fabrication includes as many as three metal layers separated by dielectric layers.
Wafer thinning, more commonly known as backlapping, is generally carried out at the end of the device fabrication process in order to reduce the fabricated wafer's thermal conductivity and to speed up signal transmission across the device. Additionally, the wafer is thinned to facilitate correct operation of microwave or millimeter wave circuits, where the wafer is normally thinned from the backside surface. A uniform (i.e., isotropic) etching process is generally needed to effectively thin the wafers to the desired final thickness.
In most cases, this involves reducing the wafer thickness from an initial 400–500 μm range down to a final range typically from 250 μm or less. In fact, current manufacturers of increasingly sophisticated and miniaturized electronic devices are demanding even thinner wafers, and therefore, 125 μm or less is now a fairly common final wafer thickness requirement.
After the last metal layer is patterned, a final dielectric layer (passivation) is deposited to protect the circuit from damage and contamination. Openings (e.g., vias) are etched in this film to allow access to the top layer of metal by electrical probes and wire bonds. Additionally, it is often necessary to provide a ground plane and ground through vias on the backside surface of the semiconductor wafer. The backside ground plane and through vias are constructed to facilitate the correct operation of microwave circuits and millimeter wave circuits.
A problem arises when it is desired to create extremely small vias on the backside surfaces of these thinned semiconductor wafers in order to establish electrical connectivity between the backside surface and the front side surface of the thinned semiconductor wafer. Conventional wet chemical etchants do not provide sufficient anisotropy to etch small backside through vias to small ground pads on the front side surface of the thinned semiconductor wafer.
Therefore, there is a need to develop systems for anisotropically etching backside through vias on semiconductor wafers, especially thinned semiconductor wafers.